Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions

The article is devoted to software bitsliced implementation of randomly generated $8\times 8$ S-Box block ciphers, focused on the use logical SIMD instructions from SSE, AVX and AVX-512 extensions in ×86-64 processors. A heuristic algorithm for minimizing non-algebraic S-Boxes three bases proposed: universal—based AND, OR, XOR, NOT, which allows any 8/16/32/ 64-bit processors; extended—based AND-NOT, ternary—based ternary logic instructions, processors with support. On average, representations these require 400/380/200 respectively. performance implementations cipher “Kalyna” using SSE/AVX/ Intel Xeon Skylake-SP processor was measured. fast alternative—non-bitsliced approach bytesliced SubBytes operation based AVX-512VBMI extension, resistant timing cache attacks—is proposed.